1. Field of the Invention
The present invention generally relates to the testing of memory structures and, more particularly, to testing of memory structures included in very large scale integrated circuits (VLSI).
2. Description of the Prior Art
Increases in integration density of integrated circuits has greatly increased the performance and functionality of the circuits which can be included on a single semiconductor chip. Increased functionality, of course requires increased circuit complexity and, at the present state of the art, many functionally differentiated regions such as adders, processors, logic arrays, buffers, decoders level converters and the like may be included on a single chip. These functionally differentiated regions are often designed to operate at different clock rates and even different voltages while being required to communicate with each other in a generally synchronized fashion.
Design of storage devices and processes for their fabrication have become quite sophisticated and have resulted in very low process cost for fabrication and very small memory cell area. Therefore it is currently practical to form even relatively large numbers of storage cells together with digital signal processing circuitry on a single chip and, moreover, use of multi-port memories for communication between functional components on a chip has proven to be extremely fast and efficient and thus has come into relatively widespread use. Such memories are generally referred to as embedded memories when included with circuits having other than a storage function on an integrated circuit chip.
Nevertheless, memory cells, particularly of the dynamic type which store data capacitively, are relatively delicate devices and may be subject to damage of deterioration after being placed in service. When such devices are used for communication and data transfer among functional regions or components, the reliability of storage becomes extremely critical to the proper operation of the entire chip. Therefore, it is desirable to test storage cells periodically or at certain operating states such as power-up of the chip in order to ascertain operability.
However, access to embedded memories for testing is often difficult, particularly where chip space and external connections are at a premium. For that reason, it is preferred to form a self-test circuit on the chip, itself. Numerous types of such arrangements are known and generally referred to as a built-in self-test (BIST) circuit or engine. Some forms of BIST circuits have been developed which allow the test sequence to be dynamically modified based on a selected test methodology. The amount of chip space which can be efficiently allocated to a BIST is very limited, generally to about 2% of the area of the storage devices to be tested. This area includes all components necessary to self-test a memory structure.
Designs of embedded memories have also been developed in several classes and forms which facilitate communication and other functions. If the data, address or control signals input to an embedded memory are derived from another embedded memory, the embedded memory is said to be dependent. Otherwise, the embedded memory is said to be independent. Where a dependent memory is present, the embedded memory supplying the data, address and/or control signal is referred to as the source while the dependent embedded memory receiving the data, address, or control signal is referred to as the sink.
Also, a memory component such as data, address or control signal of a dependent memory can be fed back to the input of the same dependent memory through logic having a function that can be arbitrarily chosen, depending on the desired operation of the memory. This type of self-dependent memory structure is referred to as a complex dependent memory structure. Where such feedback is not present the memory is referred to as a simple dependent memory structure. Two exemplary simple dependent RAM structures where one RAM provides address or data to another RAM and a complex dependent memory structure are shown in FIGS. 1A, 1B and 1C, respectively. These Figures demonstrate a high-level description of dependent memory structures and are not admitted to be prior art as to the present invention.
Because of the feedback of a memory component in complex dependent memory structures, testing is complicated and generally results in high test logic overhead, particularly for the large number of combinations of operations with which such a memory must be exercised. For example, to test multi-port memories, possible interactions such as shorts between the bit lines and address decoder of adjacent ports must be tested in addition to the traditional tests for single port memories, Moreover, it is characteristic of complex dependent memory structures to be adjacent to high speed data buses. These high speed buses must also be tested for possible shorts between them. Accessing these buses is only possible through the embedded memory structure and requires test patterns with sequential behavior since they are a part of the feedback loop in the complex dependent memory structure.
Since the BIST structure must accommodate the particular application and configuration of the memory and must be integrated in the design of the chip, programmable BIST architectures have been developed to provide different test algorithms without a requirement for modification of the basic BIST unit hardware. For example, a programmable BIST module could include a programmable BIST controller and other components to control the generation of test data, address and control signals. An exemplary microcode-based programmable BIST architecture 10 is illustrated in FIG. 2 (which is a high-level demonstration and not admitted to be prior art as to the present invention).
The memory BIST controller 20 includes a microcode-based controller and instruction decode logic in order to reduce the amount of storage required to provide the desired test signals in accordance with a memory test algorithm which is described in terms of a set of supported instructions stored in an instruction storage module 40 within controller 20. The size of the instruction store module 40 thus depends on the number of required instructions and constitute the largest contribution to area overhead of the BIST unit.
The process flow within programmable BIST controller 20 and its components is illustrated in FIG. 3 (which is also not admitted to be prior art as to the present invention). Once the test algorithm is designed and compiled as indicated at 30, 31, the programmable BIST controller is initialized with a set of instructions representing the selected test algorithm, 32, for example, through an external tester. An initial instruction is dispatched (33) to the instruction decode logic 35 unless it is the last instruction, as determined at 34 to exit the testing process. The instruction is decoded into one or more test signal patterns which are applied to the memory in sequence while the responses are collected and possibly evaluated. Then the next instruction is fetched or dispatched and the process is repeated until all instructions for generation of test patterns have been executed.
Testing of complex embedded multi-port memory structures requires an especially complex test algorithm which, in turn, requires a large number of instructions and a large microcode-based controller which, in general, cannot be provided within the 2% area overhead constraint alluded to above. Therefore, programmable BIST architectures are not efficiently applied to complex multi-port memory structures. The only alternative to the area overhead would be to reduce thoroughness of the test procedure which is not feasible due to the high reliability of the memory structure which must be assured.
Further, it should be appreciated that the design effort and cost of developing and compiling large instruction sets for programmable BIST architectures capable of testing multi-port complex memory structures and the design of BIST circuits incorporating them on a chip greatly increases chip design costs. This additional cost can be particularly appreciated since it is an underlying goal of programmable BIST circuits to permit accommodation of different circuits to be tested without redesign of the BIST controller and peripheral devices 30 such as are illustrated in FIG. 2 and which may be regarded as respective portions of the instruction decode logic for respective signals applied to the memory under test. This advantage of avoiding a need for custom hardware design is, of course, lost if the hardware design must be extensively modified to accommodate additional large numbers of instructions. Further, the provision of instructions in programmable ROM is, itself, somewhat self-defeating since the testing of such programmable ROM is also difficult if the storage space is relatively large.
It is therefore an object of the present invention to provide a programmable BIST arrangement for testing of complex multi-port embedded memory structures which is area efficient.
It is another object of the invention to provide large numbers of test instructions suitable for complex multi-port memory structures without requiring hardware modification or redesign of microcode based programmable BIST circuits.
It is a further object of the invention to provide a generalized design for a BIST circuit which can accommodate complex multi-port memory structures while minimizing design cost.
It is yet another object of the invention to provide a BIST circuit of reduced chip area for a given complexity of self-test procedure.
In order to accomplish these and other objects of the invention, a built-in self-test (BIST) arrangement for an integrated circuit and an integrated circuit including such a BIST arrangement are provided wherein the BIST arrangement includes an instruction decoder for generating test signals responsive to instructions applied thereto, a microcode instruction store for providing instructions to the instruction decoder, and a finite state machine for generating a plurality of instructions and providing them to the instruction decoder responsive to a test specific instruction being output by said microcode instruction store.
In accordance with another aspect of the invention, a method of testing a memory is provided including steps of dispatching an instruction from an instruction store, activating an instruction generator in response to a test specific instruction being dispatched from the instruction store, generating and delivering a plurality of instructions to an instruction decoder from the instruction generator, and delivering other instructions dispatched from the instruction store to the instruction decoder.
By using a finite state machine to generate instructions in parallel with delivery of stored instructions from an instruction store chip space can be much more efficiently utilized for a BIST arrangement. Further, the sequential nature of a finite state machine as it transitions from a state-to-state facilitates the generation of instructions which assist in data capture at times interspersed among test signals of a test signal sequence when test results are not otherwise accessible.
The use of finite state machines, itself, provides some economy of chip design since FSM design methodology is well-developed and chip layout can be largely automated from a relatively simple behavioral description. The architecture of the preferred form of the invention (providing the FSMs as modular instruction generators) allows re-use and economical modification of existing modules of BIST architecture modules to further reduce expense of new chip designs.